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functional description the msc iii is a component of the tv-sam featurebox and is responsible for driving the picture memory devices (tv-sams) and generating sync signals ( figure 6 ). together with the other devices of the featurebox it enhances picture quality and offers a number of special operating modes. the msc iii is set via the i 2 c bus, it being possible to switch the i 2 c bus address by hardware so that implementation of a simple frame featurebox is possible in conjunction with the signal mux supplied by the msc iii. other major output signals of the sda 9220-5, in addition to the clocks ll3x (13.5 mhz) and ll1.5x (27 mhz), are the memory-driving signals ( ra, rb, wt, re, scad, sca) and the sync signal csy for the teletext device. the horizontal sync signals (hs2, bln2) and the vertical sync signals (vs1, vs2) are also generated. type ordering code package sda 9220-5 q67100-h5087 p-lcc-44-1 (smd) memory sync controller iii preliminary data mos ic sda 9220-5 p-lcc-44-1 features l large area flicker elimination through field doubling l additional elimination of interline flicker in field mode l field switching and selection in field mode l noise and cross-color reduction l stills l 9-image display, still-in-picture, picture-in-still with different frame versions l zoom with selection of enlarged picture segment (8 x 12 positions) l pin-programmable operation without standard conversion semiconductor group 117 01.94
sda 9220-5 semiconductor group 118 circuit description the msc iii can be divided into the following function blocks ( figure 6 ): C sync-signal generator C memory controller C clock generator C i 2 c bus receiver the sync-signal generator uses signals vs and bln to produce the horizontal and vertical sync signals bln2, hs2, vs1 and vs2. it supplies the composite sync signal csy for the 100-hz teletext, the control signal mux for implementing a simple frame featurebox and the frame signal frm for inserting a colored frame in multi-picture, still-in-picture and picture-in-still modes. signal cfh is output to prevent the bottom flutter effect in the video cassette recorder mode. in operation without standard conversion (pin-programmable) signals bln2, vs2 and frm are switched from double to single line/field frequency. outputs csy and hs2 are not required in this case. the memory controller produces the driving signals ( ra, rb, wt, re) and the addresses (sar, sac) for the memory devices (tv-sams). in addition, it produces the dreq pulses used for requesting data from the picture processor during operation with reduced pictures. two refresh operations are performed in the memory for each tv line. the clock generator consists essentially of a pll which generates the internal and exported system clocks from input clock ll3 or ll1.5 and synchronizes them with the horizontal blanking signal. the msc can be set to one of the two input frequencies via input llsel. for the possible use of the featurebox as a channel scanner, the pll incorporates a crystal-controlled reference clock to ensure an undisturbed clock supply for memory output (stills sequence) during channel-switching phases. all modes (except switching off the standard conversion) are set by appropriate programming of the i 2 c bus data bytes. when the operating voltage is switched on, all bits of the associated control registers are set to 0. the address of the i 2 c bus is set with signal adr (24 h or 26 h ).
sda 9220-5 semiconductor group 119 detailed circuit description picture formats the msc forms part of a digital television system with line-locked scanning frequency. the nominal word rate is 13.5 mhz for luminance and 3.375 mhz for each of the u and v color components. the active region of a tv line is identified by the high time interval of bln. it comprises 720 pixels for luminance and 180 pixels each for u and v and is stored in its entirety. in the 50-hz standard a field consists of 287.5 lines and in the 60-hz standard of 243.5 lines. 288 lines are stored in the 50-hz standard (lines 23-310 of the first field, lines 336-623 of the second field) and 243 lines in the 60-hz standard (lines 17-259 of the first field, lines 280-522 of the second field), ( figure 1 ). in the 9-image mode a field without a frame consists of 208 pixels per line for luminance and 2 x 52 pixels per line for chrominance, with four pixels being lost for luminance and 2 x 1 for chrominance with memory or display frames. the number of lines without a frame is 84 for the 50-hz standard and 71 for the 60-hz standard. two lines less are displayed with a frame ( figures 2 and 3 ). in the picture-in-still (pis) and still-in-picture (sip) modes a field without a frame or having a display frame is of the same size as a 9-image window. with the memory frame, however, eight pixels are lost for luminance and 2 x 2 for chrominance ( figure 4 ). for generating the windows in the modes 9-image display, pis and sip the picture data are filtered horizontally and vertically in the picture processor and reduced by a factor of three. in the zoom mode a segment of the stored picture is enlarged by a factor of two by displaying each pixel twice as long and each line twice. the position of this picture segment is selectable. eight vertical and twelve horizontal positions can be set by the i 2 c bus ( figure 5 ). random interlace the phase of vs relative to hs and the active picture content is measured at the input. at the output vs2 is generated in the same phase relation to hs2 and the picture content. despite the random interlacing this means that standard picture conversion is possible without any visible interference. display raster there are three ways of displaying the field sequence: one is without interlace and two are with interlace, i.e. with a 50-hz or 60-hz interlace frequency or a 100-hz or 120-hz interlace frequency respectively. in what follows these are referred to symbolically as aaaa , aabb or baba . they are produced by a suitable sequence of the vertical sync pulses vs2 for the standard-converted video signal. the symbols a n , b n denote the vertical sync phases of the pulses (vs, vs2) referred to the horizontal blanking signals (bln, bln2), i.e. a n when the positive vertical sync edge falls within one blanking half cycle and b n when it falls within the complementary blanking half cycle. normally the input signal will be as follows: ( a nC1 , b nC1 ) ( a n , b n ) ( a n+1 , b n+1 ) with a n and b n virtually constant. figures 15, 16, 17, 18 and 19 show the sequence obtained for output signal vs2 when using one of the three operating modes.
sda 9220-5 semiconductor group 120 the standard conversion (sc) function can be activated via pin nw l the following correlation exists: low level at pin nw: mode without standard conversion high level at pin nw: mode with standard conversion if the standard conversion is switched on, there is a 100-(120-) hz field frequency in the 50- (60)-hz standard. field sequence with sc: a( a ) a( a )b( b ) b( b ) 1) field sequence without sc: a( a )b( b ) the following functions can be set on the i 2 c bus 2) interface: l still field sequence with sc and interlace: a( b ) a( a ) a( b ) a( a ) or b( a ) b( b ) b( a ) b( b ) field sequence with sc and without interlace: a( a ) a( a ) a( a ) a( a ) or b( b ) b( b ) b( b ) b( b ) field sequence without sc and without interlace: a( a ) a( a ) or b( b ) b( b ) l teletext text mode: a vt ( a ) a vt ( a ) a vt ( a ) a vt ( a ) or: a vt ( b ) a vt ( a ) a vt ( b ) a vt ( a ) teletext mixed mode: with sc a vt ( a ) a vt ( a )a vt ( b ) a vt ( b ) without sc a vt ( a )a vt ( b ) l teletext field mode: in this mode every second field is written to the field memory. the display raster is freely selectable. although the vertical resolution of the tv picture is slightly less in this mode, the lack of background edge flicker improves the visual effect in teletext mixed mode. an improvement in the picture can also be achieved with vcr signals in the special modes. it is also possible to select a particular field; this is useful for specific requests. l hs2 phase: programmable between 0 and 32 m s in increments of approx. 300 ns (for delay equalization between picture generation and deflection). l write operation delay owing to delay in the picture processor for noise reduction can be set between 0 and 14 or 16 and 30 ll3x clocks. l when the color frame is used, the picture-in-picture and multi-picture modes have to be activated without the software frame because the two are not identical. l the picture-in-picture and multi-picture modes cannot be switched on in the field mode; there may otherwise be no gray backing for the frame function, depending on the field. the field mode can only be activated one field after the picture-in-picture or multi-picture mode. 1) field content vertical sync phase referred to horizontal sync pulse (raster) 2) i 2 c bus: bus system patented by philips a( a )
sda 9220-5 semiconductor group 121 l when switching from free running to line-locked mode, the following maximum synchronization times can occur for standard signals: a) vertical synchronization at 50 (60) hz and 100 (120) hz: 220 (183) ms a) horizontal synchronization at 50 (60) hz: 100 (83) ms 100 (120) hz: 100 (75) ms device interfaces the interfaces of this device are designed to work with the csg sda 9257 and triple adc sda 9205-2, or dmsd/cgc, the tv-sams sda 9251-2x and picture processor sda 9290-5. the standard conversion function can be enabled and disabled on one pin. all other functions are set on an i 2 c bus interface. i 2 c bus interface 1. functional overview the following control signals are received on the i 2 c bus: C synchronization (exsyn) C blanking (blk) C control for frame mode (muxi, muxs) C vs noise reduction (vnr) C 50/60-hz standard (vert) C deflection raster (vdm 1-0) C field mode with field changeover (fldm, fldc, fldf) C delay compensation for write channel (wdel 4-0) C still (stb) C frame (fr) C write mode (wm 1-0) C picture position for 9-image, picture-in-picture (vpos 1-0, hpos 1-0) C zoom mode (zm) C position of zoom detail (zv 2-0, zh 3-0) C ntsc mode with 864 pixels per line (n864) C hs2 phase relation (hp 6-0) C disabling of frame display signal (frdis) C delay of frame display signal (frd 6-0) C duration of cfh signal (cfhw 3-0) C position of cfh signal (cfhp 3-0)
sda 9220-5 semiconductor group 122 2. description slave address: receiver format: s: start condition a: acknowledge p: stop condition data byte formats: the subaddress is incremented automatically. when the operating voltage is applied (power-up reset), all registers are set to 0. 001001adr function sub- address data byte d7 d6 d5 d4 d3 d2 d1 d0 control 1 00 exsyn blk muxi muxs vnr vert vdm1 vdm0 control 2 01 fldm fldc fldf wdel4 wdel3 wdel2 wdel1 wdel0 control 3 02 stb fr wm1 wm0 vpos1 vpos0 hpos1 hpos0 zoom control 03 zm zv2 zv1 zv0 zh3 zh2 zh1 zh0 hs2 phase 04 n864 hp6 hp5 hp4 hp3 hp2 hp1 hp0 frm delay 05 frdis frd6 frd5 frd4 frd3 frd2 frd1 frd0 cfh control 06 cfhw3 cfhw2 cfhw1 cfhw0 cfhp3 cfhp2 cfhp1 cfhp0 s0aaap slave address sub address data byte
sda 9220-5 semiconductor group 123 3. detailed tables control 1 (subaddress 00) synchronization control bit exsyn (d7) external synchronization (line-locked) 0 internal synchronization (free-running) 1 blanking control bit blk (d6) picture enabled 0 picture blanked 1 mux invert, mux strobe ( figure 9b shows the functional diagram of mux) control bit muxi (d5) muxs (d4) mux = l 0 0 mux toggles with vs2 (for vs1 = h change to l) 0 1 mux = h 1 0 mux toggles with vs2 (for vs1 = h change to h) 1 1 vs noise reduction control bit vnr (d3) mode 1 (window) 0 mode 2 (flywheel) 1 50/60-hz-standard control bit vert (d2) 50-hz standard 0 60-hz standard 1 deflection raster control bit vdm 1 (d1) vdm 0 (d0) aabb (with standard conversion ) ab (w/o standard conversion ) 00 aaaa (with standard conversion) aa (w/o standard conversion) 01 baba (with standard conversion) not defined (w/o standard conversion) 10 not defined 1 1
sda 9220-5 semiconductor group 124 control 2 (subaddress 01) field mode control bit fldm (d7) normal mode (both fields) 0 field mode (only one field) 1 field switching in field mode control bit fldc (d6) for fldf = l: change of field; (no reference to a specific field) 0 ? 1 1 ? 0 for fldf = h: field 1 displayed field 2 displayed 0 1 field mode feature selection control bit fldf (d5) free-running field mode without field reference 0 field mode with field reference 1 write operation delay in ll3 periods (from rising edge of bln) control bit wdel4 (d4) wdel3 (d3) wdel2 (d2) wdel1 (d1) wdel0 (d0) delay 0 to delay 14 delay 16 to delay 30 not defined 0 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 0 0 0 1
sda 9220-5 semiconductor group 125 control 3 (subaddress 02) still control bit stb (d7) moving image 0 still 1 frame control bit fr (d6) 9-image picture, picture-in-picture without frame 0 9-image picture, picture-in-picture with frame 1 write mode control bit wm 1 (d5) wm 0 (d4) normal mode (nm) 0 0 9-image picture mode (mp) 0 1 picture-in-still (pis) 1 0 still-in-picture (sip) 1 1 vertical picture position for 9th image control bit vpos 1 (d3) vpos 0 (d2) vertical position 0 0 0 vertical position 1 (not allowed for pis and sip) 0 1 vertical position 2 1 0 not defined 1 1 horizontal picture position for 9th image control bit hpos 1 (d1) hpos 0 (d0) horizontal position 0 0 0 horizontal position 1 (not allowed for pis and sip) 0 1 horizontal position 2 1 0 not defined 1 1
sda 9220-5 semiconductor group 126 zoom control (subaddress 03) x: dont care hs2 phase (subaddress 04) one step corresponds to eight ll1.5 cycles (approx. 300 ns). zoom control bit zm (d7) normal 0 zoom 1 vertical position of zoomed detail control bit zv 2 (d6) zv 1 (d5) zv 0 (d4) vertical position 0 to vertical position 7 0 1 0 1 0 1 horizontal position of zoomed detail control bit zh 3 (d3) zh 2 (d2) zh 1 (d1) zh 0 (d0) horizontal position 0 to horizontal position 11 not defined 0 1 1 0 0 1 0 1 0 1 switching in 60-hz mode (vert = 1) control bit n864 (d7) 858 pixels per line 0 864 pixels per line 1 hs2 phase control bit hp 6 (d6) hp 5 (d5) hp 4 (d4) hp 3 (d3) hp 2 (d2) hp 1 (d1) hp 0 (d0) 0 steps to 108 steps 0 1 0 1 0 0 0 1 0 1 0 0 0 0
sda 9220-5 semiconductor group 127 frm delay (subaddress 05) cfh control (subaddress 06) frm disable control bit frdis (d7) frame display signal frm enable 0 frame display signal frm disable (frm = l) 1 delay for frame display signal control bit frd 6 (d6) frd 5 (d5) frd 4 (d4) frd 3 (d3) frd 2 (d2) frd 1 (d1) frd 0 (d0) 0 ll1.5 cycles to 127 ll1.5 cycles 0 1 0 1 0 1 0 1 0 1 0 1 0 1 cfh width (h level) control bit cfhw3 (d7) cfhw2 (d6) cfhw1 (d5) cfhw0 (d4) 0 halfline to 15 halflines 0 1 0 1 0 1 0 1 cfh position before vs control bit cfhp3 (d3) cfhp2 (d2) cfhp1 (d1) cfhp0 (d0) 3 halflines to 18 halflines 0 1 0 1 0 1 0 1
sda 9220-5 semiconductor group 128 figure 1 picture format, normal mode
sda 9220-5 semiconductor group 129 figure 2 picture formats for 9-image mode
sda 9220-5 semiconductor group 130 figure 3 picture formats for 9-image mode, pis and sip with display frame
sda 9220-5 semiconductor group 131 figure 4 picture formats for picture-in-still, still-in-picture
sda 9220-5 semiconductor group 132 figure 5 zoomed picture segments
sda 9220-5 semiconductor group 133 figure 6 block diagram 1, featurebox with standard conversion
sda 9220-5 semiconductor group 134 figure 7 block diagram 2 memory sync controller
sda 9220-5 semiconductor group 135 figure 8 pin configuration (top view)
sda 9220-5 semiconductor group 136 pin definitions and functions pin no. symbol function description 1 v ssa analog ground 2 v dda analog supply voltage positive supply voltage (+ 5 v) for analog part 3 rst pll filter connecting pin for pll filter 4 te2 test pin test pin; must be connected to v ss for normal mode 5 te1 test pin test pin; must be connected to v ss for normal mode 6 te0 test pin test pin; must be connected to v ss for normal mode 7 ll1.5x 27-mhz clock 27-mhz clock for devices of featurebox generated by pll 8 nw select standard conversion standard-conversion switching; high level on this pin means that standard conversion is activated 9 sca serial clock serial clock for port a of tv-sam 10 scad serial address clock serial address clock for tv-sam 11 ll3x clock 13.5-mhz clock for the devices of the featurebox generated by pll 12 v ss digital ground 13 v dd digital supply voltage positive supply voltage 14 re row enable control signal for tv-sam 15 ra read transfer via port a of tv-sam 16 sar serial row address for tv-sam 17 rb read transfer via port b of tv-sam 18 sac serial column address and mode for tv-sam 19 wt write transfer via port c of tv-sam 20 v ss digital ground 21 wei write inhibit write-enable input for direct disabling of write operation for field memory 22 dreq data request data-request signal in 9-image mode for reduced picture data; at same time i 2 c bus sync signal for picture processor 23 resq reset output 24 resi reset input normally on v dd (active low) 25 v dd digital supply voltage position supply voltage (+ 5 v) for digital part
sda 9220-5 semiconductor group 137 26 adr address select 24 h for adr = 0 or 26 h for adr = 1 27 zm zoom signal control signal for featurebox output interface ic: supplies high level in zoom mode 28 vs vertical sync input determines vertical position of tv picture for 50-or 60-hz field frequency 29 vs1 vertical sync output; noise suppressed 30 mux mux switching switching signal for implementing simple frame featurebox 31 llsel select clock input a 27-mhz clock selected for llsel = low 32 cfh clock frequency hold for elimination of bottom flutter effect in vcr mode 33 osci crystal oscillator input 34 oscq crystal oscillator output crystal clock as reference for recovery in tuner scanning mode 35 scl serial clock i 2 c bus 36 sda serial data i 2 c bus 37 csy composite sync horizontal and vertical sync pulses for teletext device in standard-conversion mode 38 frm display frame signal control signal output for possible insertion of colored frame in multi-picture, picture-in still and still-in- picture modes 39 hs2 horizontal sync display horizontal pulse for standard-converted picture (31.25 / 31.47 khz) 40 vs2 vertical sync display vertical sync pulse for data readout 41 bln2 horizontal blank display blanking signal for identifying active picture line for data readout 42 bln horizontal blank blanking signal input; high phase identifies active picture line 43 llin input clock 13.5 or 27 mhz 44 v ss digital ground pin definitions and functions (contd) pin no. symbol function description
sda 9220-5 semiconductor group 138 absolute maximum ratings (all voltages are referred to v ss ) parameter symbol limit values unit remarks min. typ. max. ambient temperature t a 070 c storage temperature t stg C 55 125 c thermal resistance r th sa 50 k/w supply voltage v dd C 0.3 6 v input voltage v i C 0.3 6 v total power dissipation p tot 1.25 w operating range supply voltage v dd 4.5 5 5.5 v supply current digital i ddd 200 240 ma sum pins 13, 27 supply current analog i dda 2 2.3 ma pin 2 ambient temperature t a 070 c
sda 9220-5 semiconductor group 139 characteristics parameter symbol limit values unit test condition min. typ. max. input clock llin = 13.5 mhz/llsel = high or open (refer to figure 9 c) period t llin 68 74 80 ns h-pulse width t wh 25 ns l-pulse width t wl 25 ns h-input voltage v ih 2v l-input voltage v il 0.8 v input clock llin = 27 mhz/llsel = low (refer to figure 9 c) period t llin 34 37 40 ns h-pulse width t wh 10 ns l-pulse width t wl 10 ns h-input voltage v ih 2v l-input voltage v il 0.8 v input signal bln, vs, wei/reference clock: llin = 13.5 mhz (refer to figure 9c) setup time t su 14 ns hold time t ih 5ns h-input voltage v ih 2v l-input voltage v ih 0.8 v h-input current i ih C 80 C 500 m a l-input current i il C 100 C 500 m a input signal bln, vs, wei/reference clock: llin = 27 mhz (refer to figure 9c) setup time t su 7ns hold time t ih 6ns h-input voltage v ih 2v l-input voltage v il 0.8 v h-input current i ih C 80 C 500 m a l-input current i il C 100 C 500 m a
sda 9220-5 semiconductor group 140 output clock ll1.5x/reference clock: llin (refer to figure 9a) period t ll1.5x 34 37 40 ns h-pulse width t wh 12 ns l-pulse width t wl 12 ns clock skew * ) t sk 015ns load capacitance c l 50 pf h-output voltage v qh 2.4 v i qh = C 2.5 ma l-output voltage v ql 0.4 v i ql = 5 ma output clock ll3x/reference clock: llin (refer to figure 9a) period t ll3x 68 74 80 ns h-pulse width t wh 25 ns l-pulse width t wl 25 ns clock skew * ) t sk 015ns load capacitance c l 50 pf h-output voltage v qh 2.4 v i qh = C 2.5 ma l-output voltage v ql 0.4 v i ql = 5 ma *) with steady-state pll. characteristics (contd) parameter symbol limit values unit test condition min. typ. max.
sda 9220-5 semiconductor group 141 output clock sca/reference clock: ll1.5x (refer to figure 9a) h-pulse width t wh 10 25 ns l-pulse width t wl 10 ns clock skew ** ) t sk 015ns load capacitance c l 50 pf h-output voltage v qh 2.4 v i qh = C 2.5 ma l-output voltage v ql 0.4 v i ql = 5 ma period t sca1 34 37 40 ns normal mode with standard conversion t sca2 *** ) 68 74 80 ns normal mode without standard conversion or zoom mode with standard conversion t sca3 *** ) 136 148 160 ns zoom mode without standard conversion output clock scad/reference clock: ll3x (refer to figure 9a) period t scad 34 37 40 ns h-pulse width t wh 12 ns l-pulse width t wl 12 ns clock skew * ) t sk C 15 0 ns load capacitance c l 50 pf h-output voltage v qh 2.4 v i qh = C 2.5 ma l-output voltage v ql 0.4 v i ql = 5 ma * ) with steady-state pll and provided that the capacitive load of the reference clock is identical or more. ** ) with steady-state pll and provided that the capacitive load of the reference clock is identical or less. *** ) t sca2/3 are generated from t sca1 (by blanking the high phases). characteristics (contd) parameter symbol limit values unit test condition min. typ. max.
sda 9220-5 semiconductor group 142 output signals: bln2, frm, zm, hs2, vs2/reference clock: ll1.5x (refer to figure 9b) delay time (for hs2, vs2) t qd 20 ns delay time (for bln2, frm, zm) t qd 25 ns hold time t qh 6ns load capacitance c l 30 pf h-output voltage v qh 2.4 v i qh = C 2.5 ma l-output voltage v ql 0.4 v i ql = 5 ma output signals: wt, rb, csy, vs1, mux, dreq, cfh/reference clock: ll3x (refer to figure 9b) delay time t qd 25 ns hold time t qh 6ns load capacitance for wt, rb c l 50 pf load capacitance for csy, vs1, dreq, cfh c l 30 pf h-output voltage v qh 2.4 v i qh = C 2.5 ma l-output voltage v ql 0.4 v i ql = 5 ma output signals: ra/reference clock: sca (refer to figure 9b) delay time t qd 15 ns hold time t qh 0ns load capacitance c l 50 pf h-output voltage v qh 2.4 v i qh = C 2.5 ma l-output voltage v ql 0.4 v i ql = 5 ma characteristics (contd) parameter symbol limit values unit test condition min. typ. max.
sda 9220-5 semiconductor group 143 output signals: sar, sac, re/reference clock: scad (refer to figure 9b) delay time for sar, sac t qd 25 ns delay time for re t qd 20 ns hold time t qh 6ns load capacitance c l 50 pf h-output voltage v qh 2.4 v i qh = C 2.5 ma l-output voltage v ql 0.4 v i ql = 5 ma pll-filter currents charge current i ch 80 250 m a v ql = 1.9 v charge current i ch 70 250 m a v ql = 2.9 v discharge current i dch C 80 C 300 m a v ql = 1.9 v discharge current i dch C 70 C 300 m a v ql = 2.9 v filter elements (see figure 10a) c f1 ? 1.5 nf, r f ? 1.8 k w , c f2 ? 100 pf crystal (see figure 10b) nominal frequency f q 6.7500 mhz effect of temperature and accuracy of adjustment d f / f q temperature range t a 070 c load capacitance c l 33 0.5 pf resonant impedance z r 60 w equivalent parallel cc o 7 20 % pf crystal load 0.1 mw characteristics (contd) parameter symbol limit values unit test condition min. typ. max.
sda 9220-5 semiconductor group 144 figure 9 timing diagram (for characteristics of sda 9220-5)
sda 9220-5 semiconductor group 145 a) filter circuitry b) crystal circuitry figure 10 circuit configuration for filter and crystal reset behavior of sda 9220-5 the circuitry has sensor logic for separately detecting values below the minimum supply level on the v dda and the two v dd pins. a reset cycle is initiated whenever such values are detected; the reset time is preset by charging and discharging the pin capacitance of the reset input pin which is not normally connected. this time can be extended by connecting resi with an external capacitance. the resi pin can also be connected directly with a signal; a res low level enables reset, a res high level terminates the reset. the internal circuit reset status is output via reset resq and can then be used as an active low signal (low level = reset status). during the reset phase all the output clocks generated by msc (ll1.5x, ll3x, sca and scad) are kept at low level. upon completion of the reset the sda 9220-5 is in its basic (line-locked) mode. if no clock is applied to llin at this point of time, the vco in the pll oscillates at its free-running frequency (5C20 mhz) and enables all the output clocks derived from it. C typical control values for the reset system initiation level for reset on v dd v ddr < 3.9 v low level on resi v ril < 1.5 v high level on resi v rih > 2.3 v output low level on resq v ql 0.4 v ( i ql = 5 ma) output high level on resq v qh 3 2.4 v ( i qh = C 2.5 ma)
sda 9220-5 semiconductor group 146 figure 11 application circuit for eliminating bottom flutter
sda 9220-5 semiconductor group 147 figure 12 timing diagrams, horizontal sync signals for standard conversion note: the figures indicate the number of ll3-clock periods
sda 9220-5 semiconductor group 148 figure 13 timing diagrams, horizontal sync signals without standard conversion note: the figures indicate the number of ll3-clock periods
sda 9220-5 semiconductor group 149 figure 14 memory basic cycle for normal mode with standard conversion and 864 pixels per line wtn: CCC write operation delay 0 or 16 ll3x clocks ----- write operation delay 1-14 or 17-30 ll3x clocks
sda 9220-5 semiconductor group 150 figure 15
sda 9220-5 semiconductor group 151 figure 16
sda 9220-5 semiconductor group 152 figure 17
sda 9220-5 semiconductor group 153 figure 18
sda 9220-5 semiconductor group 154 figure 19
sda 9220-5 semiconductor group 155 operation with standard conversion figure 20a vs/vs2 phase relation for mode a( a ) a( a ) b( b ) b( b ) and vs edge in first bln-half cycle (vnr bit = 1)
sda 9220-5 semiconductor group 156 figure 20b vs/vs2 phase relation for mode a( a ) a( a ) b( b ) b( b ) and vs edge in second bln-half cycle (vnr bit = 1)
sda 9220-5 semiconductor group 157 figure 21 timing diagram, csy-pulse sequency b) start of tv line 3 (1st field) or 316/266 (2nd field) before standard conversion (50/60 hz) c) start of tv line 3 of each field after standard conversion (100/120 hz) *) alternative **) rising edge of csy comes four ll3x cycles before falling edge of bln2
sda 9220-5 semiconductor group 158 figure 22 timing for i 2 c bus parameter symbol limit values unit min. max. clock frequency f scl 0 100 khz inactive time before start of new transmission t buf 4.7 m s hold time for start condition (after this time first clock pulse is generated) t hd; sta 4.0 m s low clock phase t low 4.7 m s high clock phase t high 4.0 m s setup time for data t su; dat 250 ns rise time for sda and scl signals t tlh 1 m s fall time for sda and scl signals t thl 300 ns setup time for scl clock in stop condition t su; sto 4.7 m s all values are referred to specified input levels v ih and v il .

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